On Fri, 30 Mar 2001, Hársfalvi, Levente wrote: > BTW I've just found something interesting. The sound output of the > Plus/4 is pulse width modulated, the PWM running at the dot clock of the > computer. The period is 16 or 32 dot clock cycles when both channels are > on or just one channel is on, respectively; (in the latter case, the > 'second' of the two phases is kept constant 0, 'halving' the average > duty). The duty cycle grows as '1 - 3 - 5... - 15' as function of volume > level 1,2,3...8. Indeed. I noticed this with an oscilloscope some months ago, and have been promising to do some proper quantitative measurements, but somehow never got around to it. > However, there's something strange: the 'end point' of the duty cycle is > always 'late' by the time of approximately one master clock cycle time. > This delay is constant, it is not a function of the master clock :-O. > > Check this. In NTSC mode, dot clock = master clock/2. When measuring the > PWM signal of volume level 1 ($ff11=$91), I should get '2' as duty cycle > (since my unit is the master clock). Instead, the result is '3'. If I > halve the master clock for the Plus/4, I should get two times the > previous one, '4' - I get '5' instead. When I quarter the clock, the > 'theoretical' result is 8, and I get '9'. ...Should there be an internal > delay 'unit' somewhere in this part of the TED? ...It should be > something like this, but why on Earth?... The theory I came up with while examining the scope traces was that the rise time of something internal to TED is different to its fall time. This is characteristic of NMOS anyway, so that sounds reasonable. Unfortunately it all departs from the nice theoretical, digital-friendly model of PWM with integer clock cycle mark-space times. Richard --this message went through the email@example.com emailing list---
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