Hi Richard, >On the plus/4, DATA is output from bit 0 of the 8501 I/O port (inverted) >and CLK from bit 1. However, DATA is read in from bit 7 whereas CLK is on >bit 6 - ie. the order of the signals is reversed. Thanks for the info. To complete the picture, where is ATN connected to? >Yes, you can tell the plus/4 to run at the slower speed and this is >constant except for TED chip badlines. However bear in mind that this is >somewhat slower than the C64's near 1MHz, so if the routines rely on the >drive processor (1MHz) remaining roughly in sync with the computer >processor for a certain minimum number of cycles then you may have >problems. Is there a "screen blanking" mode or something which keeps the TED running at constant speed? - Nick PLEASE TAKE NOTE: The contents of this email (including any attachments) may be privileged and confidential. Any unauthorised use of the contents is expressly prohibited. If you have received this email in error, please advise us immediately (you can contact us by telephone on +61 8 9441 2311 by reverse charge) and then permanently delete this email together with any attachments. We appreciate your co-operation. Whilst Orbital endeavours to take reasonable care to ensure that this email and any attachments are free from viruses or other defects, Orbital does not represent or warrant that such is explicitly the case (C) 2000: Orbital Engine Company (Australia) PTY LTD and its affiliates - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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