RE: JIffyDOS Coding
Date: 2001-03-28 03:43:10

Hi Richard,
>On the plus/4, DATA is output from bit 0 of the 8501 I/O port (inverted)  
>and CLK from bit 1. However, DATA is read in from bit 7 whereas CLK is on
>bit 6 - ie. the order of the signals is reversed.
Thanks for the info. To complete the picture, where is ATN connected to?

>Yes, you can tell the plus/4 to run at the slower speed and this is
>constant except for TED chip badlines. However bear in mind that this is
>somewhat slower than the C64's near 1MHz, so if the routines rely on the
>drive processor (1MHz) remaining roughly in sync with the computer
>processor for a certain minimum number of cycles then you may have
Is there a "screen blanking" mode or something which keeps the TED running
at constant speed?

- Nick


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