Hi, I hope to have both the CPU and the VIC have access to all 16 megs or more, but working with SDRAM is a total nightmare. The stuff needs four cycles to set up for even the first transaction and then can be bursted out at 133 mhz one per cycle, however if you need totally random access(which the vic needs)then it takes the 133 mhz bandwidth and divides it by six == 22 mhz bandwidth. I may have to add sram cache and burst 64k at a time in and out. I'm not worried about the SDRAM at this point. I have my prototype using the only real memory sram's :) Jeri Bryan Pope wrote: Will the 16MB of memory be directly accessible by both the 6502 and SuperVIC? Or will we have video RAM and CPU RAM?Bryan-This message was sent through the cbm-hackers mailing list.To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi. __________________________________________________ Do You Yahoo!? Yahoo! Auctions - Buy the things you want at great prices. http://auctions.yahoo.com/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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