Re: How does NTSC VIC-II produce 65 cycles per line

From: Michiel Boland <michiel_at_boland.org>
Date: Thu, 12 Jan 2023 18:11:26 +0100
Message-ID: <6261f41d-dec3-98ac-e3bc-3719ab8e610b_at_boland.org>
On 1/12/23 13:52, silverdr_at_srebrnysen.com wrote:
> 
> 
>> On 12 Jan 2023, at 12:21, Michiel Boland <michiel_at_boland.org> wrote:
>>
>> Hi. The PAL VIC-II chip has 9 bits for the X coordinate. That can accommodate 504 pixels (63 cycles) per line. I would assume that the NTSC VIC-II also has only 9 bits for X coordinate. Then how does that chip manage to produce 65 cycles per line? Since 520 pixels would require 10 bits.
> 
> FWIW - a number of cycles per line (in every version) do not output any pixels

Just had an idea (this always happens 5 minutes after I post something :) )

The upper 6 bits of the X counter are implemented as a low-ripple counter with 
reset line, so that it can reset to 0 for PAL. The reset line and increment 
lines are connected internally (the increment input is inverted.)

If you disconnect the reset part, but keep the increment, you can in theory gain 
an extra cycle by bringing the increment line low at a strategic point. The 
tricky bit would be to time it in such a way that the timer does not stop 
incrementing altogether.

It appears that sprite positions $180 and $187 are duplicated; there is a 
noticeable jump if you move a sprite from $187 to $188. So I suspect there is 
some magic in the chip that stops the X counter from incrementing around X=$180.

Cheers
Michiel
Received on 2023-01-12 19:00:02

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