Re: Theorizing: chip select lines... (continued after mistake)

From: tokafondo_at_tokafondo.name
Date: Wed, 22 Jun 2022 23:37:25 +0000
Message-ID: <a12d4d31f6458d4a26231d7fcf149e77_at_tokafondo.name>
22 de junio de 2022 22:15, "Jesus Cea" <jcea_at_jcea.es> escribió:

> On 22/6/22 21:24, tokafondo_at_tokafondo.name wrote:
> 
>> YIKES!!! I pressed 'sent' by mistake and didn't had completed the post!!!
> 
> Remember than RAM is accessed twice per cycle: CPU and VIC-II.

AFAIK, they both take turns when accessing memory. Only when VIC-II asserts BA/AEC low, it takes both turns for itself (badlines or sprite data fetching).


> 
> If I would design a fast 6502-like accelerator I would interpose a fast
> cache (write thru with a small (maybe 1-2-4 bytes) write buffer) or,
> using something like a 65816, fast and exclusive RAM in other banks.
> 
> Dynamically adjusted 6502 frequency will not get you anything useful,
> because 6502 do a memory cycle per CPU clock, always, even when not
> useful at all. Too complicated, too little gain.

One CPU cycles takes 500ns. Wouldn't be actually that useful that one CPU would take 125ns, so a 'batch' of four CPU cycles could be run while the VIC-II waits for its turn to take on memory again?

I agree that it's too complicated to get it done, because now I'm realizing that if all the support chips (CIA, SID) are rated at 1Mhz, you wouldn't be able to mix several clock changes during those 500ns that the VIC-II waits for its turn for take on the bus again.

Somehow, the clock dynamic control system would have to know in advance if the memory accesses by the CPU were going to be done to the memory or to the support chips, so it could change the clock rate accordingly but most importantly, in sync with the system bus. If not done that way, it could happen that the CPU would access the memory at 4Mhz and then try to switch to 1Mhz during high phi2, and then those memory fetches or writes wouldn't be completed at all. Simply put, 4 x 125 ns = 500ns, but 125ns + 500 ns > 500 ns, so the memory transaction would get interrupted and bus contention would happen yes or yes.


> 
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Received on 2022-06-23 02:00:09

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