Re: 1571/1581 Sources: Macro WDTEST inserting NOP before reading WD177x status register / writing command register

On 3/24/22 21:45, Spiro Trikaliotis wrote:
> Hello,
> 
> * On Fri, Mar 11, 2022 at 05:41:27PM +0100 I wrote:
>> Hello,
>>
>> I am trying to understand the sources of the 1571 and 1581 drives.
>>
>> In the original drive sources of the 1571 and 1581 (as found on
>> zimmers.net), there is a macro WDTEST:
>>
>> WDTEST  .macro
>>          .ife <*!.$03
>>          nop
>>          .endif
>>          .endm
> 
> It seems
> 
> 1. I am not the first one who discovered this macro and made guesses as
>     to what its purpose is: http://forum.6502.org/viewtopic.php?f=2&t=4382;
> 
> 2. that the people there came up with the same idea like My guess, that
>     it has to deal with the data register (cf. "Dr. Jefyll" starting on
>     "Tue Jan 31, 2017 2:11 am"), which was later corrected;
> 
> 3. that changing the sources to remove the NOP does not change the
>     behaviour of the 1581: (cf. "flobbydust", "Sat Feb 18, 2017 10:34 am").
> 
> 
> As the code is already there with the 1571, it might be a hardware
> glitch that was to be prevented that does not exist on the 1581. Or it
> might be something that happens very seldom.
> 
> I looked at the data sheets of the WD1770/WD1772, the 6502 and the
> schematics of the 1581:
> 
> The -CS for the WD177x is generated as: -CS = -(PHI2 AND NOT -WDSEL)
> (cf.
> http://www.zimmers.net/anonftp/pub/cbm/schematics/drives/new/1581/1581-16.gif)
> with a 74LS00,
> and
> 
> -WDSEL = is the output of a 74LS139 decoder with A13=A14=1 and A15=0),
> connected directly to the 6502 output (cf.
> http://www.zimmers.net/anonftp/pub/cbm/schematics/drives/new/1581/1581-15.gif)
> 
> So, the -CS is gated directly with PHI2 through a 74LS00. The maximum
> propagation delay of it is 15 ns.
> 
> For the WD177x, T_AH (address hold after -CS is going high) is minimum
> 10 ns.
> 
> For the 6502, the t_ADH (address hold after PHI2 falls) is minimum 30 ns.
> 
> Thus, when PHI2 falls, at most 15 ns later, -CS is de-asserted. Thus,
> t_ADH of the 6502 guarantees that it will be stable for at least 15 ns,
> which is enough for the T_AH of the WD177x.
> 
> I do not see any problems with this on the 1581.
> 
> 
> For the 1570/1571, it is different (cf. marked schematics at
> https://spiro.trikaliotis.net/download/1571-wd177x.png):
> 
> The -CS of the WD177x is generated through a 74F32 (a 2-Input OR gate)
> and pin 17 (-CS1) of the 20 pin gate array (marked in red), and PHI1 (!
> - marked in green).
> 
> 
> So, it seems that the "wild guess" of Frank is right! I did not find any
> numbers in the 6502 data sheet of when PHI1 goes high after PHI2 goes
> low, but it seems to be later than PHI2. It must be later, because
> otherwise, PHI1 and PHI2 would be overlapping.
> 
> So, the time to react for the -CS of the WD177x is shortened. This might
> explain why Commodore used a 74*F*32, which has a shorter propagation
> delay (max of around 7 ns) than a 74LS32 or 74LS00, but it could be that
> this is still not enough!

Maybe... But how would a NOP help with that? You still end the access 
too early, the NOP will not prolong it since the bus timing is 
determined by hardware and cannot be influenced by software. Besides, 
before the 6502 can execute that NOP, it needs to load it, which needs a 
bus cycle.

The NOP only makes sense if there is something happening inside the 177x 
that needs a bit of extra time to finish before the next access to 
whatever register can happen.

  Gerrit