Re: 6510 I/O port as chip selects to expand memory

The 7501/8501 used in the C264/plus4 series sacrificed one of the port 
bits internally to add the infamous GATE_IN logic.

The rest of the chip layout is identical to the 8500 (==6510).

Here's a solution which uses a 6502 instead of the 6510 to mimic the 
8501 functionality:

https://gitlab.com/toms01/6502a_or_w65c02_at_8501



On 18/11/2021 12:10, Julian Perry wrote:
> Re: 6510 I/O port as chip selects to expand memory Hello smf,
>
> Thursday, November 18, 2021, 9:19:02 PM, you wrote:
>
> *> The 6510 only actually has 6 bits, the 6510-1 & 6510-2 have 8 bits.
>
> > Be careful how you design it, the 6509 based cbm2 pretty much did what
> > you're suggesting and programming them was terrible.
>
> > On 17/11/2021 23:01, Claudio Sánchez wrote:
>
> >> Can this I/O port be used in a new design as chip select for memory
> >> banking?
>
>
> *From what I've read, internally the 6510 was a full 8 bit I/O, but 
> the last 2 bits were not wired through, due to the 40pin packaging DIP 
> limitation: there were simply not the pins spare. There is no NMI in 
> the 75/8501 - a severe limitation IMHO, losing edge-detected interrupt 
> capability.
>
> I've seen comment that early C264 series development used a 
> custom-packaged 6510, with the extra pads wired through to utilize the 
> extra 2 present, but unused pin (one, used for cassette I/O)
> I've also seen repairs for the notoriously fragile 8501 replaced with 
> a C64 6510, and a replumbed BIOS to allow at least normal tape I/O 
> routines hacked to use bits from the more restricted 6bit I/O space of 
> the 6510.
>