Re: FPGA using Python language

Maybe we are talking the same thing but due to the word choices are causing confusion. Yes, there are logic gates / cells or elements but they have to be configured by the bitstream file (little binary file) before it is functional to do anything other whatever maybe a "brick-proofing" measure where there is an explicit default core built into a piece of non-volatile memory on the FPGA chip as a failsafe mode.

However, FPGAs isn't new stuff. I remember this stuff and conversations about FPGA and the models I mentioned like those used in the ol' CommodoreOne / C-One project and that era. They aren't exactly pre-configured with any sort of core. 

Some of the newer FPGAs have some on-board "core" that it boots into unless you load in a core. A way to sort of "factory reset" your FPGA and it be still functional. 

I'm not surprised they would do that these days. Just like we do this kind of measure to prevent our newer motherboards from becoming brick because you flashed the bios and botched it and now have a dead BIOS chip requiring you to remove the BIOS and reflashing it with a ROM burner using another computer.... or replacing the BIOS chip if you didn't want to go through the trouble. 

Yeah, some of these cores using some kind of ARM IP. That's another matter perhaps. The old ACEX 1K30 didn't have a whole lot of logic cells or elements or whatever it was called. They didn't necessarily have any kind of on-board flash so you needed some means of loading the flash memory data into the core using the dedicated I/O pins that had a dedicated purpose during initialization to loading a bitstream from a compatible flash memory through that type of interface. 



> On 02/23/2021 6:13 AM smf <smf_at_null.net> wrote:
> 
>  
> On 22/02/2021 21:49, admin_at_wavestarinteractive.com
> admin_at_wavestarinteractive.com wrote:
> 
> > FPGAs without any core loaded is "turing nothing" because they are blank with no logic or gates configured to do anything.
> 
> FPGA aren't blank, the logic gates are all there waiting for the i/o to
> be hooked up & there is enough logic to be able to load a bit stream
> into ram. That is enough to be turing complete, I'm not talking about
> running a turing complete language on the FPGA itself.
> 
> You used to have to design chips by hand, now you can emulate an ASIC on
> an FPGA before you bake it.
> https://www.xilinx.com/applications/emulation-prototyping.html
> 
> Eventually tools will evolve so you don't need to think about all the
> things you currently have to think about because it's cheaper.
> 
> Whether that is using an existing language concept or something new is
> an implementation detail, but existing concepts are more useful for the
> same reason steering wheels and pedals are similar on all cars.