On Wed, Aug 26, 2020 at 9:07 AM Baltissen, GJPAA (Ruud) <ruud.baltissen_at_apg.nl> wrote: > > Jim Schreef: > > Never thought that buying slower ICs would fix issues,.... > > But why does it go wrong? AFAIK the 6502 reads the data at the end of the upper half of PHI2 and IMHO a faster ROM should not make any difference. Am I overlooking something? as I have already written in a previous answer in this thread, the likely problem is hold data time at the end of the cycle (falling phi2). 6502's datasheet indicates 10ns minimum hold time on a 1 MHz read cycle after phi2 falling edge. Some fast memories could have a shorter hold time. HTH Frank IZ8DWFReceived on 2020-08-26 10:01:59
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