Re: DMA successes with Verilog

From: David Wood <jbevren_at_gmail.com>
Date: Fri, 12 Jun 2020 23:50:28 -0400
Message-ID: <CAAuJwioNcNzoF2MYHAKfyLuX3uf=wPpAkQa3Ac3rGs=qu1YV8w_at_mail.gmail.com>
Here's a screenshot from my logic analyzer while I was working with
_dW on his DMA issues.
https://cdn.discordapp.com/attachments/634910231838720010/677600872087289876/unknown.png
Unsure if links or attachments are more acceptable. :)

Note phi2 (red), and ras/cas (also red; green) labels on left.  Analog
channel b2 is also connected to phi2.  This is a 8-pin-video breadbin
board running an ntsc 6567r9

-jbev

On Fri, Jun 12, 2020 at 11:14 PM laubzega <mileksmyk_at_gmail.com> wrote:
>
> Jim Brain wrote
> > I thought the VIC-II did the CAS cycle during PHI2=low half of the
> > cycle.    I can put it on the LA tonight, but is there a diagram already
> > available showing the signals?
>
> How about the last page of this document:
> http://archive.6502.org/datasheets/mos_6567_vic_ii_preliminary.pdf
>
> M.
>
>
>
> --
> Sent from: http://cbm-hackers.2304266.n4.nabble.com/
>
Received on 2020-06-13 06:02:22

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