RDY and 8500 (was: Differences between 8501R1 and 8501R4)

From: laubzega <mileksmyk_at_gmail.com>
Date: Fri, 12 Jun 2020 22:27:18 -0500 (CDT)
Message-ID: <1592018838454-0.post_at_n4.nabble.com>
Let me do some thread necromancy to ask about this very well known paragraph
from Gideon's freezer document:

"It was attempted to pull –DMA low around 250 ns before the falling edge of
PHI2, so
after the R/–W line had stabilized. This works perfectly on a 6510, but
makes the 850x
CPU in a C64c crash. Apparently, this CPU does not like to see RDY ‘true’ on
a rising
edge of PHI2, and ‘false’ on the subsequent falling edge."


We have clocked hundreds of testing hours with BeamRacer running on several
8500s. Not a single crash, despite stopping and restarting the CPU exactly
in this manner up to 200 times per frame.

Has anyone actually experienced the issue described by Gideon? Could the
fact that we are pulling down just the RDY (as opposed to RDY and AEC he had
to manipulate jointly with the DMA line) have any significance?

Thanks,
Milek




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Received on 2020-06-13 06:02:05

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