Re: Accessing the C64 memory between 65xx chips operations.

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Sun, 19 Apr 2020 21:07:07 +0200 Message-ID: <ad4b16b9-856d-221d-744e-cb35dfdc5f50_at_laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 4/19/20 8:53 PM, André Fachat wrote:
> 
> So say you have a 4MHz capable SRAM, every second cycle could be used for
> the second CPU, and the other cycles would be used by the CPU and VIC.

No... only the CPU has the AEC pin. VIC does not. It keeps it's address 
lines offline during the CPU part of the cycle, but during its own cycle 
it hogs the bus and you cannot take it off. Also, VIC multiplexes its 
addresses internally, you cannot affect that timing.

So, unless you want to REALLY redesign the whole system, you can only 
use the CPU part of the cycle and split it. And even that needs quite a 
bit of changes to the system.

  Gerrit