Re: Dynamic RAM / memory expansion
Date: 2001-01-20 01:28:05

On Fri, 19 Jan 2001, Ruud Baltissen wrote:

> Hallo David,
> Thanks for answering.


> RAS has to be activated for CAS. See:
> This document (and
> others) mentions self-refreshing DRAMS, ie the ones with in-build counters.
> But then, how do I know which DRAM has (or not)?

Any modern SIMM will have that ;)

> Another problem is the 72 pin SIMM. It has a 32 bit wide bus. Nice if you
> have a 486. But the 65xx is 8 bits wide. Is it possible to select just 8
> bits? If not, 24 bits are waisted unless one knows a way to preserve the
> data during a write-action.

The same way the machines that are made for those simms do while doing
8bit accesses.

Do this:
On a0-a1, put a 2-4 converter in, and feed each output to CAS0 CAS1, CAS2,
and CAS3 respectively.  When you do a single byte access (I.E. every time
in the c64), only one CAS line is asserted, and thus only one byte of ram
is accessed. ;)

A0-A1 never make it to the simm by the way ;) A2->A16 (or more?) go to the
row/col decoder for addressing the rams properly.

wide (>8bit) simms are handy in that they have a CAS line (or is it
ras? one or the other) for each bank of 8 bits, plus another for the
parity bit(s).  Even the high and mighty powerPC must sometimes make a
1-byte-wide access to ram *wink*.


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