Hallo David, Thanks for answering. > Refreshing most 256k chips/simms, by the way, is exteremely simple. All > you have to do is flash CAS (or Ras? cant remembr) alone, and it'll > refresh the correct row, and update the counter accordingly (one that's > INCIDE the ram) RAS has to be activated for CAS. See: http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?dynamic+RAM This document (and others) mentions self-refreshing DRAMS, ie the ones with in-build counters. But then, how do I know which DRAM has (or not)? Another problem is the 72 pin SIMM. It has a 32 bit wide bus. Nice if you have a 486. But the 65xx is 8 bits wide. Is it possible to select just 8 bits? If not, 24 bits are waisted unless one knows a way to preserve the data during a write-action. Groetjes, Ruud http://home.hccnet.nl/g.baltissen/index.htm - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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