On Mon, 20 Nov 2000, Nicolas Welte wrote: > The 2MHz bit disables most of the VIC-IIe's memory accesses (probably > it simply tristates the bus), but it does not blank the screen. It tristates the address bus, but not the data bus. And the memory refresh cycles (5 per line) are still there. So, you'll get 2*65-5=125 cycles per line on NTSC and 2*63-5=121 cycles per line on PAL. Actually it's possible to display graphics on the 2MHz mode screen, since the VIC-IIe displays whatever the 8502 does on the bus. > Also, the VIC-IIe will keep doing the memory refresh accesses on each > scanline and this causes a slowdown to 1 MHz for I think five cycles > on each line. Also it'll switch to 1 MHz mode when you try to access $dxxx during the "wrong" half-cycle. Marko - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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