Yes, I implemented this mode for full speed SRQ nibbling in the ZoomFloppy with a 1571. I clock data out at 2 MHz with the max speed (500 Kbit/sec) as well as in from the microcontroller. There’s a diagram with my oscilloscope showing this in this presentation: http://root.org/~nate/c64/xum1541/ZoomFloppy20100918.pdf It is stable though we’ve occasionally found a few 6526A CIAs that would get errors at this clock rate. The Amiga model seems to be more stable for this. To reset the shift register, you can just reprogram the mode (I think). I know it works fine with no data persistence when I switch from input to output mode, for example. -Nate > On Oct 28, 2019, at 3:48 AM, Michał Pleban <lists_at_michau.name> wrote: > > Hello! > > The 6526 datasheet says that the maximum speed of the shift register is > PHI2/4, but it is not clear whether it means it only in output mode > (because the serial clock rate is tied to timer B, and this is the > highest frequency you can get from it), or also in output mode. Does > anyone know what is the real maximum rate in input mode? If I have a > 2MHz CIA, would it be safe to assume that it can accept an input clock > in the 2MHz range? > > Also, is there any method to reset the shift register to a safe state? > Because if there is not, then any spurious pulses on the CNT line could > make the shift state go out of sync without any means to restore it? > > Regards, > Michau. >Received on 2020-05-29 23:22:30
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