On 7/10/2019 1:06 PM, Michał Pleban wrote: > Jim Brain wrote: > > > But the 6509 does have a SYNC pin, and I thought you have used it? It's the 6502 I used, and the code went through so many revisions, it got hidden. Yep. I do use it. But, the idea of a state machine like the Verilog uses still would work. Sync or not, the state machine for the entire opcode matrix would be large, probably too large for a CPLD. And, if you're doing an FPGA, might as well just replace the CPU with the FPGA. JimReceived on 2020-05-29 22:28:46
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