Re: DMA successes with Verilog

From: Jim Brain <brain_at_jbrain.com>
Date: Thu, 21 Jun 2018 12:15:31 -0500
Message-ID: <11654a4a-7681-0c11-7289-a70a9b3b75d1@jbrain.com>
On 6/21/2018 10:57 AM, smf wrote:
> On 20/06/2018 17:53, Jim Brain wrote:
>> One of the ideas is to wait for a write and then init the DMA, but 
>> Spiro is noting that some writes are followed by more writes that 
>> will get lost if we try to start the DMA after the first write.
>
> Ok, I get it now.
>
> According to Gideon you wait for a write followed by a read, then you 
> know the next cycle will be a read.
>
> http://codebase64.org/lib/exe/fetch.php?media=base:safely_freezing_the_c64.pdf 
>
>
> ultimax nmi + irq might be something else to consider
>
>
But, in that doc (which I referenced), he notes that his plan fails if 
the code does only reads.  We can debate how likely that would be (I 
personally like the idea of watching BA, and just ensuring the screen is 
on), but it's a valid corner case.


-- 
Jim Brain
brain@jbrain.com
www.jbrain.com
Received on 2018-06-21 20:01:47

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