Re: DMA successes with Verilog

On 20/06/2018 17:53, Jim Brain wrote:
> One of the ideas is to wait for a write and then init the DMA, but 
> Spiro is noting that some writes are followed by more writes that will 
> get lost if we try to start the DMA after the first write.

Ok, I get it now.

According to Gideon you wait for a write followed by a read, then you 
know the next cycle will be a read.

http://codebase64.org/lib/exe/fetch.php?media=base:safely_freezing_the_c64.pdf

ultimax nmi + irq might be something else to consider