Re: DMA successes with Verilog

From: Pasi 'A1bert' Ojala <*a1bert_at_iki.fi*> Date: Thu, 21 Jun 2018 13:19:16 +0300 Message-ID: <c37f1b9b-d2de-4bd3-47d5-2a6a3642478a@iki.fi> · a1bert_at_iki.fi

On 21.06.2018 11:19, Michał Pleban wrote:
> Gerrit Heitsch wrote:
>
>> After looking at the schematics, I think the only surefire way would be
>> to wait for the end of a badline or sprite access and then take over the
>> bus. That way VIC has done the heavy lifting for you, the CPU has been
>> halted properly.
> But when the display is turned off, that is not gonna happen, right?
If both the display and all sprites are turned off, then VIC-II doesn't 
steal the bus.
> Regards,
> Michau.
-Pasi