Re: DMA successes with Verilog

Gerrit Heitsch wrote:

> After looking at the schematics, I think the only surefire way would be
> to wait for the end of a badline or sprite access and then take over the
> bus. That way VIC has done the heavy lifting for you, the CPU has been
> halted properly.

But when the display is turned off, that is not gonna happen, right?

Regards,
Michau.