OK, next try ... answering to the list ... sorry. > I also have images from my scope which show the same behaviour. What's > left now is to explain that behaviour. > > Gerrit The TED system manual of which scans were presented here some time ago explains the behaviour quite well including timing diagrams. It correspondens to the HDL implementation if I understand it correctly. See chapter 5.5.2: * R/W from the 6502 core is put through transparently to the R/W pin if MUX is HIGH and is latched when MUX is LOW. * If MUX goes back to HIGH the latch is released and the (maybe meanwhile changed) R/W-signal from the core is put through again. This is why you think you see a change at the rising edge. IMHO it is not edge triggered but a transparent latch. * If MUX goes HIGH when AEC is LOW then R/W is changig to HIGH-Z until AEC is HIGH when MUX is changing from LOW to HIGH. See also chapter 5.4: "If AEC is low when Gate In [a.k.a MUX, remark] makes a low to high transition, the R/W line will go to a high impedance until the next transition of the Gate In line and AEC is high prior to the transition." The not-so-complete version (I think) of that manual can be found here: https://www.pagetable.com/docs/ted/TED%20System%20Hardware%20Manual.pdf Anyway chapters 5.4 and 5.5.2 are present there, too. Regards kinziReceived on 2018-06-18 22:00:04
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