On 06/18/2018 08:00 PM, Jim Brain wrote: > On 6/18/2018 9:54 AM, Gerrit Heitsch wrote: >> On 06/18/2018 10:04 AM, Jim Brain wrote: >>> Is there a document that explains the purpose of MUX/GATE_IN? Why >>> did the 264 series need to latch the R/W line and why did they need >>> to do it in the CPU in such an inefficient way? >> >> The reason, as I understand it, is to make sure that R/W stays LOW >> long enough during a write cycle. Remember, the 264 does switch the >> CPU to double clock if TED doesn't need the bus. AEC is HIGH all the >> time during that period. This means that all signals from the 7501 are >> suddenly active only half as long. >> >> Most RAMs don't seem to care since people have reportedly used 6510 in >> an adapter with R/W connected directly without issues. >> >> Maybe Bil can shed some light on it? Assuming he reads this... >> >> I have captured write cycles on the logic analyzer. R/W depends on MUX >> and can only change state with the rising edge of MUX. Mail me if you >> want the images. >> >> Gerrit >> >> >> >> > I do want them, but it would be best, I think, if you could host them > somewhere for all of us. I am sure I cannot be the only person stymied > by this signal and it's purpose. I don't really have webspace I could use... But feel free to use the images as you like. > Your statement about R/W can only change as MUX rise seems different > from the HDL and guidance previously given. How do we verify this? I also have images from my scope which show the same behaviour. What's left now is to explain that behaviour. GerritReceived on 2018-06-18 21:03:16
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