Re: 6502 to 7501/8501 converter

From: Hegedus, Istvan <hegedusis_at_t-online.hu>
Date: Sun, 17 Jun 2018 21:42:37 +0200
Message-ID: <0e4d0d5a-031b-8399-097e-74f6d67507e9@t-online.hu>
On 2018.06.17. 19:16, Gerrit Heitsch wrote:
> On 06/17/2018 07:11 PM, Jim Brain wrote:
>> On 6/17/2018 3:58 AM, Gerrit Heitsch wrote:
>>> On 06/17/2018 09:18 AM, Jim Brain wrote:
>>>> I think someone was wanting this: https://github.com/go4retro/Fake7501
>>>
>>>
>>> Under 'Theory', you wrote the following:
>>>
>>> The 6502 address, data, and r/w lines are fed through the CPLD so 
>>> they cna be optionally tri-stated, and the on-board PIO port bits 
>>> 0-6 are emulated.
>>>
>>>
>>>
>>> The 7501/8501 has Bit 0-4 and 6 and 7 on the PIO port, Bit 5 is the 
>>> missing one. This makes it easy to use BIT commands when reading data.
>> I meant to say "lines", so I updated.
>>
>> I also added some as yet untested Verilog HDL to implement the 
>> functionality.  Comments appreciated.  he datasheets left at least 
>> one item ambiguous (to me, at least)
>>
>>   * I assume the 7501/85xx is derived from the 6510 core, and the 6510
>>     DS says address/data/and r/w are tristated when aec is used, but the
>>     7501 DS says only address is tristated.
>
> Well, data needs to be tristated as well or there would be problems 
> with TED using the bus.
>
> R/W is a slightly different thing on the 7501 since there is some 
> magic involved with the R/W line and the MUX signal.
>
>  Gerrit
>
assignr_w_7501 =(aec ? r_w_6502 : 'bz); I am missing here the GATE IN 
signal. That needs to be added just like I added it in FPGATED.  A 
transparent latch is needed to keep r_w_6502's previous state when GATE 
IN (MUX) is low. When MUX is high and AEC is not low r_w_7501 can be 
r_w_6502.
I would do the following (assuming gate_in is an input and r_w_latched 
is a register).

reg r_w_latched;

always @(gate_in,r_w_6502)
    begin
     if(gate_in)
         r_w_latched=r_w_6502;
    end

assign r_w_7501 = (aec ? r_w_latched : 'bz);

Istvan
Received on 2018-06-17 22:00:03

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