On 06/17/2018 07:11 PM, Jim Brain wrote: > On 6/17/2018 3:58 AM, Gerrit Heitsch wrote: >> On 06/17/2018 09:18 AM, Jim Brain wrote: >>> I think someone was wanting this: https://github.com/go4retro/Fake7501 >> >> >> Under 'Theory', you wrote the following: >> >> The 6502 address, data, and r/w lines are fed through the CPLD so they >> cna be optionally tri-stated, and the on-board PIO port bits 0-6 are >> emulated. >> >> >> >> The 7501/8501 has Bit 0-4 and 6 and 7 on the PIO port, Bit 5 is the >> missing one. This makes it easy to use BIT commands when reading data. > I meant to say "lines", so I updated. > > I also added some as yet untested Verilog HDL to implement the > functionality. Comments appreciated. he datasheets left at least one > item ambiguous (to me, at least) > > * I assume the 7501/85xx is derived from the 6510 core, and the 6510 > DS says address/data/and r/w are tristated when aec is used, but the > 7501 DS says only address is tristated. Well, data needs to be tristated as well or there would be problems with TED using the bus. R/W is a slightly different thing on the 7501 since there is some magic involved with the R/W line and the MUX signal. GerritReceived on 2018-06-17 20:02:23
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