Re: Strange 8255 behavior

Den Sat, 16 Jun 2018 00:29:10 -0500 skrev Jim Brain <brain@jbrain.com>:
> On 6/15/2018 10:22 PM, Mia Magnusson wrote:
> >
> > Maybe it would be easiest to implement data port A in one CPLD and
> > the rest in another? Afaik data port A doesn't have any
> > dependencies on the other parts of the CIA except address decoding,
> > while everything else has some kind of dependences.
> A quick compilation here notes that 2 8 bit IO ports with individual
> DDR pins (and the mux to read all 4 data values) takes 40
> macrocells.  32 for the IO, and 1 macrocell for each muxed read bit.
> Thus, I predict half the 6526 will take more than a 64/72 macrocell
> CPLD, meaning a 128/144 won't work, and 2 128/144 units or a 128/144
> and a 64/72 would be required if not a 256/288 macrocell unit.
> Financially, a 256/288 is cheaper, so I am not sure I see a financial
> case for splitting up the logic.

Agree.

Something might worth investigating is if would be financially
reasonable to use a 6522 VIA for the 16 I/O pins (but route two through
the CPLD for the options to use PB6/PB7 for special purposes) and let
the CPLD emulate the rest of the CIA.

In the end it might be more expensive but we don't know that until it's
investigated :)

> > It is rather important that the key decoding actually works. A
> > device with symmetrical drive capability would be far from ideal.
> > It might be neccesary to have two pins for each CIA port pin, one
> > that inputs and drives outputs low, and one that solely drives
> > output high which in fact would more or less just be connected to
> > the other pin and the CIA replacement pin with a series resistor.
> If NMOS drives hard to ground and not very hard to +5V, you *might*
> be able to get by with letting the pins float high via 1K resistors
> and drive only to ground with the CPLD (Xilinx has tristate output
> buffer options, and I am sure the rest do as well)

Yeah, resistors would work, or perhaps even better some kind of simple
current mirror / current generator so the drive is more equal over the
voltage range the output can be at depending on the load. Iirc you
would only need one transistor for each output plus a (zener) diode for
reference.


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