Re: Strange 8255 behavior

From: Jim Brain <brain_at_jbrain.com>
Date: Sat, 16 Jun 2018 00:29:10 -0500
Message-ID: <87ee4257-a2e6-16f5-2fd5-8dfc14365bab@jbrain.com>
On 6/15/2018 10:22 PM, Mia Magnusson wrote:
>
> Maybe it would be easiest to implement data port A in one CPLD and the
> rest in another? Afaik data port A doesn't have any dependencies on the
> other parts of the CIA except address decoding, while everything else
> has some kind of dependences.
A quick compilation here notes that 2 8 bit IO ports with individual DDR 
pins (and the mux to read all 4 data values) takes 40 macrocells.  32 
for the IO, and 1 macrocell for each muxed read bit.  Thus, I predict 
half the 6526 will take more than a 64/72 macrocell CPLD, meaning a 
128/144 won't work, and 2 128/144 units or a 128/144 and a 64/72 would 
be required if not a 256/288 macrocell unit.  Financially, a 256/288 is 
cheaper, so I am not sure I see a financial case for splitting up the 
logic.
> It is rather important that the key decoding actually works. A device
> with symmetrical drive capability would be far from ideal. It might be
> neccesary to have two pins for each CIA port pin, one that inputs and
> drives outputs low, and one that solely drives output high which in
> fact would more or less just be connected to the other pin and the CIA
> replacement pin with a series resistor.
If NMOS drives hard to ground and not very hard to +5V, you *might* be 
able to get by with letting the pins float high via 1K resistors and 
drive only to ground with the CPLD (Xilinx has tristate output buffer 
options, and I am sure the rest do as well)

Jim


-- 
Jim Brain
brain@jbrain.com
www.jbrain.com
Received on 2018-06-16 08:00:04

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