On Tue, Jun 12, 2018 at 4:08 PM, Jim Brain <brain@jbrain.com> wrote: > On 6/12/2018 2:24 PM, David Wood wrote: > >> TL;DR - >> A RMW operation should be possible without modifying anything but the r/w >> signal on the bus according to most FPM datasheets I've studied, but would >> require some pretty good timing to ensure the VIC-II has completed its CAS >> cycle since the cart has to run blind relative to RAS and CAS. It's >> already capable of counting DOT cycles so that should be easy. >> > I thought the VIC-II did the CAS cycle during PHI2=low half of the > cycle. I can put it on the LA tonight, but is there a diagram already > available showing the signals? > I'm not aware one that anyone has officially published. I think Zero-X had done a timing grab at high resolution when trying to figure out how memory corruption occurs during a VIC-II DMA restart though. If that's still in the wild it could be used to gather information. It's probably simpler to just grab your own sample. Publishing what you find would be really interesting to see. :) That said, there has to be a RAS/CAS sequence during PHI2=low so the VIC-II can read graphics data from memory. During text mode I believe most accesses usually head for the ROM, but with a RAM charset or bitmap mode that wouldn't be the case. A second RAS/CAS sequence has to occur during PHI2=high to complete a transaction for the CPU. > > Jim > > >Received on 2018-06-13 00:02:13
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