Re: DMA successes with Verilog

On 6/12/2018 2:24 PM, David Wood wrote:
> TL;DR -
> A RMW operation should be possible without modifying anything but the 
> r/w signal on the bus according to most FPM datasheets I've studied, 
> but would require some pretty good timing to ensure the VIC-II has 
> completed its CAS cycle since the cart has to run blind relative to 
> RAS and CAS.  It's already capable of counting DOT cycles so that 
> should be easy.
I thought the VIC-II did the CAS cycle during PHI2=low half of the 
cycle.    I can put it on the LA tonight, but is there a diagram already 
available showing the signals?

Jim