Den Wed, 14 Mar 2018 00:24:59 +0000 (UTC) skrev Steve Gray <sjgray@rogers.com>: > Saleae make a nice 16-line logic analyzer if you have a real machine > to connect it to. I don't have any real B machine. But the thing I really want to investigate is how the maximum and minimum values for the delays in the involved parts combine > I've looked at the B schematics hundreds of times and I can't follow > the timing logic ;-) This is where some kind of timing analysis software would come in handy. Each single line in itself isn't that hard to follow, it's the large amounts of signals that makes it hard to grasp. U65, the shift register, together with U56, an 8-input NAND gate, creates a 9 stage ripple counter (similar to 4022, 4017). Dot clock controls this, so it cycles through at 2MHz and each output is acive 1/9th of a the cycle time of 2MHz, i.e. 1/9 of 500ns, about 56ns each. Various 7474's are used to generate all the different outputs together with the dot clock and inverted dot clock. Some of the magic happens because in some places it's 74S74's and in some places it's 74LS74's. Also the simpler gates are also a mix of LS and S logic. It's also made more complicated by the fact that most of this logic is on sheet 2, but it partially continues on sheet 1. IMHO this whole circuit kind of screams that it wants to be redone some other way :) > The rest of the machine is pretty straight forward. Yeah, except dram refresh while in 8088 mode :) > Anyway, transcribing the schematics to Kicad is a cool project. Good > luck! Steve Thanks! -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-03-14 22:40:44
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