Re: Hardware emulation of 6509 using 6502?

From: Michał Pleban <lists_at_michau.name>
Date: Wed, 14 Mar 2018 13:21:10 +0100
Message-ID: <5AA913B6.4080008@michau.name>
Hello!

Mia Magnusson wrote:

> To fully understand how the B works, I think I need some kind of
> software to make timing diagrams. I don't know if any such software
> exist, I've actually been tinkering with the idea to use project
> planning software as the min/max delay time in each gate could be
> treated as min/max time for a task in a project, and how signals depend
> on previous delays can be treated like how a task in a project depends
> on earlier tasks to finish. That would only display one full CPU cycle
> though, but that is probably no problem.
> 
> The timing generation on the B is IMHO an example of bad engineering.
> The basic idea is sound, to divide the 18MHz dot clock by 9 with a shift
> register wired up as a ring counter and use those outputs to control
> stuff. However some stuff looks horrible like they use 74*74 flip flops
> hooked up with one output connected to it's set or reset input to
> create a short spike on the outputs each time a pulse reaches the clock
> input. This makes the function really depending on gate times not only
> being fast enough but also slow enough (!).

Can't it be simulated with something like PSpice?

Regards,
Michau.
Received on 2018-03-14 22:42:14

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