Re: Hardware emulation of 6509 using 6502?

From: Segher Boessenkool <segher_at_kernel.crashing.org>
Date: Sun, 25 Feb 2018 17:29:28 -0600
Message-ID: <20180225232927.GQ21977@gate.crashing.org>
On Sun, Feb 25, 2018 at 05:08:34PM -0600, Jim Brain wrote:
> On 2/25/2018 4:09 PM, Segher Boessenkool wrote:
> >
> >After the rising edge of Phi2 you still have Tmds (the setup time),
> >something like 75ns on a 2MHz part, before the data bus is stable.
> >
> >You're supposed to read the data bus at the *falling* edge of Phi2 (and
> >you have at least 30ns there; Thw, the hold time).
> I understand what I am supposed to do, but the 1650 is showing me 
> otherwise.  Maybe the HP1650 is too old and takes more than 30nS to 
> sample the pins on a falling edge.  I have a 34 channel USB LA here, and 
> I can see about hooking it up.
> 
> If I sample at falling edge on the 6509, I *also* see the $96 on the 
> databus at step 24 (sta $96), when it should be $06 on the bus

Ah, I missed that, sorry for the noise.

> If I switch to rising edge, I see $06 (and the later $91/$b1 stuff)
> 
> No matter where I sample on the 6502, I get $96 at that point on the 
> databus.  The data lines are directly connected from the 6502 to the 
> 6509 socket, so the CPLD is not involved.  In fact, at this point, the 
> CPLD is not doing anything.


Segher

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Received on 2018-02-26 01:02:07

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