On Sun, Feb 25, 2018 at 9:01 PM, Jim Brain <brain@jbrain.com> wrote: > Right now, even forgetting the PORT register, the 6502 is deviating from the > 6509 in operation right after reset. > > https://github.com/go4retro/Fake6509/blob/master/ref/6509%20versus%206502.pdf > > Left side is 6509, right is 6502. > > R/W, A0-15, D0-7,PHI2 are all bridged. > > https://github.com/go4retro/Fake6509/blob/master/pcb/Fake6509_v2%20Schematic.pdf > > PORT is set to output $f (15) as per datasheet. > > The system goes along fine until the CMP $03fa at $f99e. The 6509 reads > $f0, while the 6502 reads $f8. After a bit, the paths greatly diverge. I > think I am out of my element, and need help to move beyond this. I don't think that's the main difference, that's a read maybe from RAM? I don't really know what's mapped at $03FA (I wish I had a CBM-II), but the next instruction is a BNE, and if I'm following the machine code correctly, then A contains A5 (A9 A5 = LDA #A5), so the BNE should branch regardless of F0/F8 difference. PC does increment on the 6509 side on the BNE instruction and that doesn't seem correct to me, how does it read D0 on both $F9A1 and $F9A2 then read 07 also at $F9A2? Maybe some missing synchronism on your analyzer setup? Anyway, it seems it goes on the same path there. Where it's really wrong is on the writes: Step 0022, A contains #06, it has been loaded before with A9 06 (LDA #06) then there a STA $96 (85 06), so step 0024 is the actual write and it's correct on the 6509 side (address 0096, data 06) and wrong in the 6502 side (address 0096, data 96). So there's something really wrong on what is put on the data bus during on a write. If you look at the other writes, data is wrong also and it's always the last read data, not the actual data that should go on the bus for the write. HTH Frank IZ8DWF Message was sent through the cbm-hackers mailing listReceived on 2018-02-25 22:00:30
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