Den Sat, 24 Feb 2018 12:01:47 -0700 (MST) skrev Dr Jefyll <laughton@cyg.net>: > Luckily that's pretty easy. But if page crossings are allowed then > things get harder, because when cycle 6 arrives it might be the data > access or it might be the opcode fetch of the next instruction. We > need to know whether or not to flip to P3-P0 flip back to their > previous state -- and there can't be any mistake about this! So, > what I'm saying is: allowing page crossings on cross-bank accesses > requires extra resources. Isn't the sync signal good enough? The possible risk/problem I see is if the flipping of P0-P3 is too slow so they bounce when they are supposed to be stable. Especially the DRAMs are sensitive to this. I'm not sure if they are used in the RAS and/or CAS part of a DRAM access cycle. Let's hope they only control CAS, then it's less of a problem and there is also far more room for slow timing. -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies. Message was sent through the cbm-hackers mailing listReceived on 2018-02-25 01:01:24
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