Re: testing 6550s outside a 6502 bus

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Thu, 4 Jan 2018 19:09:09 +0100 Message-ID: <33d5bf8d-f98d-8c01-75eb-7ffe8eba8941@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 01/04/2018 06:56 PM, Francesco Messineo wrote:
> Hi all,
> as I'm repairing a 2001 320008 assy, I'm trying to test the 6550s and
> 6540s on a microcontroller board that I've made.
> I would use a real 6502, but I've only one spare left, so that's not
> an option :)
> 
> It seems that the 6550 latches the selects, address and R/W line (for
> example lowering R/W after PHI2 L->H always results in a read cycle)
> on the rising edge of PHI2, but still I can't make a correct read or
> write cycle.

How much time before the rising edge of PHI2 did you set up the address 
lines? There might be a minimum (and maybe maximum...) setup time for 
the address lines before PHI2 can go high.

  Gerrit

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