> On 2017-11-06, at 21:35, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: > >>> I see XCLKEN go only to the 74F258 on the A500+ schematics. And if you think about it, you don't really need external resync, you can use hsync and vsync in output state to sync up with the source by varying the clock supplied to the system until everything matches. Kind of a PLL. >> That's exactly what I understand Mia wrote and I rephrased: "Meaning you have to slow down or speed up the Amiga clock and wait for the syncs to align their phases. This takes time. Not much but still. Then you need to constantly monitor the two for drifting and react accordingly by either speeding up or slowing down - basically a form of PLL." >> If that's how it actually works then I stand corrected. I (and as I understood smf too) thought it was done by supplying the reference pulses to Amiga so that it "knows" when to start the line/field. I thought that was the purpose of having the possibility of sync pins to act as inputs. > > That might have been the intention at the beginning, but it's likely that the PLL idea worked better once properly implemented since it means the whole system is synchronized to your clock source. I am still not 100% convinced that this is the way it is done. I'd be willing to try and make sure what's happening there, and I should still have two or three Amiga genlocks left from the times I used them but I remember that they remained because they were all broken.. I think I should have three somewhere. A Commodore one, a GVP and Electronic Design. > Of course, maybe they did flip that bit in Software too, without the schematics of a Genlock or the Videotoaster, we'll never know. But do we know what's the result of flipping the bit? If flipping the bit and supplying pulses makes the Amiga sync to them? Well... -- SD! - http://e4aws.silverdr.com/ Message was sent through the cbm-hackers mailing listReceived on 2017-11-07 09:00:47
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