On 02/18/2017 09:38 AM, groepaz@gmx.net wrote: > On Saturday 18 February 2017, 08:24:26 smf <smf@null.net> wrote: >> On 17/02/2017 20:26, Gerrit Heitsch wrote: >>> That can be fixed by using a static RAM instead of DRAMs. >> >> It can be fixed by latching signals as well. >> >> My point is that a 100% VIC II in an FPGA would have the VSP problem, or >> it's not 100%. AFAIK vice doesn't have the VSP problem either. > > actually x64sc can emulate it :) (its optional, "VSP Bug Emulation" in VICII > settings) > > and no, the problem can _not_ be fixed (only) by using SRAM - that was tried > and proven wrong long ago. its an urban myth that doesn't want to die :) Well, the VSP-Problem happens because DRAMs use destructive readout, meaning even a read cycle has to write the data back to the cells. This happens inside the DRAM once /RAS goes high. This is not the case with SRAM, a read cycle will just read the contens of a cell without destroying them. So when you have a problem with address lines changing while /RAS goes down and your latch latches the wrong address, you might read the wrong data, but you CANNOT destroy the RAM contents this way as you can with DRAM when you confuse the row decoder. I have done a SRAM replacement for the C64 using a 128KB SRAM, a 74HCT573 and a 74HCT32 and so far no one was able to detect the VSP bug when using it. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2017-02-18 12:00:03
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