> On 2016-12-23, at 01:33, Ingo Korb <email@example.com> wrote: > > firstname.lastname@example.org writes: > >> Or any tools that would actually work and let me translate >> synthesizable VHDL designs into GAL JEDEC files. > > IIRC Lattice ispLEVER Classic can do that. Yes - in theory. In practice it is one of those that don't "actually" work. I already spent some sizeable amount of time trying to find answers why it doesn't do what's expected. Like here: https://groups.google.com/d/msg/comp.lang.vhdl/ISVk3-TVpTM/Q6L92vmgDQAJ It basically outputs: ******* Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro ' Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. Version : 2.0.00.17.20.15 Done sucessfully with exit code 1. Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 Done: failed with exit code: 0002. ******* and so far nobody's been able to tell me why or how to make it not to. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-12-23 11:00:02
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