Re: Free (as in freedom) FPGA development tools

From: Rainer Buchty <>
Date: Thu, 22 Dec 2016 23:19:03 +0100 (CET)
Message-ID: <alpine.DEB.2.02.1612222245090.7371@localhost>
On Thu, 22 Dec 2016, wrote:

> BTW I am still stuck with my search for working set of free like in 
> speech tools that would allow me to program some SPLDs (CPLDs later). 
> Or any tools that would actually work and let me translate 
> synthesizable VHDL designs into GAL JEDEC files.

VHDL for GALs will be hard to find. The former Xilinx Webfitter had a 
VHDL frontend that could be used together with a GAL (and CPLD) fitter, 
but unfortunately that was discontinued several years ago and AFAIK 
never released as download software.

If you find something that creates logic equations from VHDL input, you 
could eventually translate them to be fed into PALASM1.5, WinCUPL or 
OpalJr which all are freely available these days.

In any case, you will most likely require some sort of translator script 
that creates proper PALASM or CUPL from the flattened logic equations 
the VHDL synthesizer (hopefully) outputs.

Given the low complexity of S/CPLDs, though, I don't think you'll gain 
much there from using VHDL over CUPL. (PALASM is more rudimentary but ok 
if you just want to do basic equations, truth tables, or state machines. 
Using PALTOGAL.EXE you can convert the JEDEC files from PAL/PALCE to 


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Received on 2016-12-22 23:00:03

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