Re: MAX Machine PLA equations

From: Segher Boessenkool <>
Date: Sat, 6 Aug 2016 09:09:51 -0500
Message-ID: <>
Hi Michał,

On Sat, Aug 06, 2016 at 01:30:20PM +0200, Michał Pleban wrote:
> > The I/O part becomes
> >  [...]
> > which seems sane, except for the VIC accesses to VIC and CIA.  
> Yes, that got my attention too. Looking at the Excel with the truth
> table, it is evident that nVIC and nCIA are driven in the VIC address
> space where it does not make any sense. Maybe it's some kind of error
> the designers made, and nobody noticed (or nobody bothered)?

Right, that makes sense...  Except SID is treated "properly"!

> > What drives A15,A14 during such accesses, anyway?
> Good question. I can't see anything in the schematic that could drive
> them. Maybe that's not very relevant, since the VIC memory map seems to
> repeat itself every 16 kB.

But not the 6703 equations!


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Received on 2016-08-06 15:00:02

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