Re: MAX Machine PLA

From: Segher Boessenkool <>
Date: Sun, 31 Jul 2016 09:29:17 -0500
Message-ID: <>
On Sun, Jul 31, 2016 at 02:38:00PM +0200, Michał Pleban wrote:
> > It decodes the top 6 address lines and the BA signal (from VIC, it says
> > if VIC resp. the CPU is doing a memory access) to the various chip select
> > signals (ROML ROMH VIC SID COLRAM CIA RAM EXRAM), forces all VIC accesses
> > to reads, and connects D0..D3 to D8..D1 for CPU accesses to the colour RAM.
> So it looks like it's not a PLA, but rather a 4-bit buffer + address
> decoding logic.
> Looking at the schematic, I see 9 inputs: A10..A15, CLK0, BA, R/W in
> And 9 outputs: /ROMH, /ROML, /COLRAM, /CIA, /SID, /VIC, /EXRAM, /RAM,
> R/W out + there might me some additional internal signal(s) needed to
> drive the 4066.

D0..D3 are inputs too, and D8..D11 are tristate outputs.  There is no
real 4066 functionality I think (only one direction is needed).

> Would that be correct? I am not really sure whether CLK0 should be an
> input, but I think it is the PHI0 signal coming out of the VIC?

Yeah, the clock is an input I think.


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Received on 2016-07-31 15:00:02

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