Re: MAX Machine PLA

From: Michał Pleban <*lists_at_michau.name*> Date: Sun, 31 Jul 2016 14:38:00 +0200 Message-ID: <579DF128.8000008@michau.name> · lists_at_michau.name

Hello!

Segher Boessenkool wrote:

> It decodes the top 6 address lines and the BA signal (from VIC, it says
> if VIC resp. the CPU is doing a memory access) to the various chip select
> signals (ROML ROMH VIC SID COLRAM CIA RAM EXRAM), forces all VIC accesses
> to reads, and connects D0..D3 to D8..D1 for CPU accesses to the colour RAM.

So it looks like it's not a PLA, but rather a 4-bit buffer + address
decoding logic.

Looking at the schematic, I see 9 inputs: A10..A15, CLK0, BA, R/W in

And 9 outputs: /ROMH, /ROML, /COLRAM, /CIA, /SID, /VIC, /EXRAM, /RAM,
R/W out + there might me some additional internal signal(s) needed to
drive the 4066.

Would that be correct? I am not really sure whether CLK0 should be an
input, but I think it is the PHI0 signal coming out of the VIC?

This would mean that the login could be easily implemented in a 22V10
PAL, once the interal equations are figured out.

Regards,
Michau.

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