Re: FPGATED

GODIL vs CRAIGNELL  installed on the socket of the TED of a C116 motherboard

http://netfilters.eu/craignell-1.JPG
http://netfilters.eu/craignell-2.JPG

the craignell is plugged  on the socket  (no idea if it can replace a 
ted, not checked)


http://netfilters.eu/godil-1.JPG <http://netfilters.eu/craignell-1.JPG>
http://netfilters.eu/godil-2.JPG <http://netfilters.eu/craignell-1.JPG>

the godil is not completely plugged a capacitor is blocking it



On 16/07/24 12:28 PM, Hegedűs István wrote:
> Hi,
>
> Thanks for this info! Good to know it. I will check those craignell ones!
> Thanks
> Istvan
>
>
> -----Original Message----- From: didier derny
> Sent: Sunday, July 24, 2016 7:03 AM
> To: cbm-hackers@musoftware.de
> Subject: Re: FPGATED
>
> Hi,
>
> beware about the GODIL, I have some, but I lost a lot of time with
> defective GODIL sold by trenz-electronic...
> replaced several month later by oho-electronic but I lost a lot of 
> time....
>
> the GODIL is quite big if you place one inside a plus4 or C116 it
> becomes impossible to close it...
> I was trying to replace a 6530 for KIM1 (project abandoned all my time 
> lost)
>
>
> you can also try:
> https://www.enterpoint.co.uk/products/obsolete-component-replacement/craignell-1/ 
>
> or
> https://www.enterpoint.co.uk/products/obsolete-component-replacement/craignell-2/ 
>
>
> but beware for the craignell the GND and VCC pin are not remappable you
> have to specify the position
> when you order.
>
> I'm often using a craignell-1 28 pin as eprom when I'm developping
> (quickly reprogrammed via jtag, without the need to remove the chip /
> erase / reprogram/ reinstall)
>
> I had several problems....
> -  problems with the level shifters
> -  problems of delay
> -  problems with glitches to filter
>
> On 16/07/23 11:27 PM, Hegedűs István wrote:
>> Hi,
>>
>> I believe that should be much easier. It can be done in a GODIL (I 
>> just don't have one but I will buy).
>> My FPGATED has the 8501 shell written around fpga64's 6502 core. It 
>> is a good starting point however I have to think how to implement 
>> hold times when the FPGA runs on phi0 instead of the higher 28MHz 
>> (4*dor clock) internal clock.
>> Othe roption is to synchronize the FPGA clock to phi0. Probably that 
>> is the way to go. I will work on it later.
>>
>> Istvan
>>
>>
>> -----Original Message----- From: Gerrit Heitsch
>> Sent: Friday, July 22, 2016 4:45 PM
>> To: cbm-hackers@musoftware.de
>> Subject: Re: FPGATED
>>
>> On 07/22/2016 02:16 AM, Steve Gray wrote:
>>> Very nice! I'm looking forward to a drop-in replacement. I have a few
>>> Plus/4's that could use a new TED.
>>
>> Next project would be a replacement 8501 since those also die easily...
>>
>>  Gerrit
>>
>>
>>
>>       Message was sent through the cbm-hackers mailing list
>>
>>       Message was sent through the cbm-hackers mailing list
>
>
>       Message was sent through the cbm-hackers mailing list
>
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