Re: MOnSter 6502

From: Segher Boessenkool <>
Date: Mon, 30 May 2016 07:47:08 -0500
Message-ID: <>
On Mon, May 30, 2016 at 11:40:03AM +0000, Baltissen, GJPAA (Ruud) wrote:
> The reason for using the extra adders was that, what ever I tried, I needed more cycles than the 6502 when using the 8 bits ALU as adder. After introducing the adders, I found out I could be faster than the 6502. So I then wondered (and still do) how the 6502 handled indexed operations.

Say, instruction b5, lda zp,x .

The first two cycles are the last two cycles of the previous insn (there
is a lot of pipelining); at the start of T2, the second instruction byte
(the ZP address) is on the data bus (the first byte is tored in the IR,
the instruction register).

DL is the data latch, for reading from the data bus.
DB, SB, ADL, ADH are the internal data buses.
ABL, ABH are the (two halves of the) address buffer, writing to the
external address bus.
ADD are the ALU inputs and output.
AC is the A (accumulator) register.

  -- T2
  DL -> ADL -> ABL
  00 -> ADH -> ABH
  (this does a dummy read from the zp)
  X  -> SB  -> ADD
  DL -> ADL -> ADD
  compute the sum

  -- T3
  ADD -> ADL -> ABL
  (and this now reads the correct address)

  -- T0
  (fetch the first byte of the next instruction)
  DL -> DB -> SB -> AC
  (set flags NZ from DB)

  -- T1
  (fetch the second byte of the next instruction)


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Received on 2016-05-30 13:00:02

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