RE: MOnSter 6502

From: Baltissen, GJPAA (Ruud) <>
Date: Mon, 30 May 2016 11:15:49 +0000
Message-ID: <>
Hallo Marko,

> In case anything that is incompatible with the NMOS 6502 is considered an error, I could offer two candidates.
> (1) The BCD mode is not clearly covered.
> ...
> The instruction decoder ROM should be able to represent any illegal opcodes just fine.  

To start with the Instruction Decoder ROM: in this case I use EEPROMs. As input they use the Opcode, a counter and various state signals like Reset, NMI, IRQ and whether a branch should be taken or not. IMHO _every_ opcode can be programmed, step by step, thus also steps that actually are just a waist of time. And with "every opcode" I thus also mean illegal opcodes. But I haven't studied them very well and there may be some exceptions: illegal opcodes that make various registers output their data at the same time. IIRC SAX (Store A and X) does this. And that could ruin my 74ALS573 latches.

Regarding the BCD: when I started with the design I first had the idea to use the well known 74181 ALUs. Until I ran into the BCD mode. And that is when I decided to use two EEPROMs as ALU as well. If you have a look at the schematics you will seen that one of the inputs is the decimal flag. And again it is just a matter of programming these EEPROMs to behave like the ALU inside the 6502.

I just mentioned TWO EPROMs. And yes, this ALU is 16 bits, thus four EEPROMs. The original design had only two but then I needed something to handle indexed commands and the first design had extra adders to take care of this. But the I thought about a 16 bits ALU because:
a) a 16 bits ALU could solve the needed additions as well
b) I needed much less parts
c) as bonus I could think of 16-bits operations (65816)

I hope this clears the matters.

Met vriendelijke groet / With kind regards,
Ruud Baltissen

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Received on 2016-05-30 12:00:02

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