Re: MOnSter 6502

From: Marko Mäkelä <>
Date: Mon, 30 May 2016 13:11:09 +0300
Message-ID: <20160530101109.GB2224@x220>
Hi Ruud,

On Mon, May 30, 2016 at 07:00:08AM +0000, Baltissen, GJPAA (Ruud) wrote:
>> Its not quite as accurate though.
>And what is not accurate, if I may ask? IMHO the schematics cover every 
>possible aspect of the 6502. But if I'm wrong, please tell so I can 
>correct the error(s).

The description hints that the aim was a similar level of compatibility 
as the 65C02, which is not a bad goal either.

In case anything that is incompatible with the NMOS 6502 is considered 
an error, I could offer two candidates.

(1) The BCD mode is not clearly covered. (Maybe you simply ignored it, 
because it has very little practical use.)

(2) The ALU is mentioned to be 16 bits. Could the added dummy cycles 
(to remain speed-compatible with a NMOS 6502) be accessing different 
addresses than a NMOS 6502? What about lda $ff,x or jmp ($xxff)?

Other than these potential incompatibilities, I do not see any 
fundamental reason why the TTL6502 would be incompatible with the 
observable behaviour of the simulation. The instruction 
decoder ROM should be able to represent any illegal opcodes just fine.  
(Those undocumented instructions whose exact behaviour depends on 
temperature or other external conditions would work deterministically in 
both simulations.)


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