On 4/25/2016 8:24 AM, Mark McDougall wrote: > On 25/04/2016 1:33 AM, firstname.lastname@example.org wrote: > >> There seem to be a kind of a pattern emerging from what I read around >> the net: people who begin or do a little / occasionally / hobbyists >> tend to prefer Verilog as "easier", "more familiar", "more concise". >> People who do a lot of this / do it for living seem to gravitate >> towards VHDL. > > In my _personal_ observations, I'd say that it's easier to write bad > code in Verilog than it is in VHDL. I don't tend to see a lot of bad > VHDL, but I've seen some shocking Verilog, though perhaps that's > merely a symptom of your observation above?!? As one of the former group of people, I would say that it's not that we want to write bad Verilog, we just want to want to focus on other things. That said, at least I am happy to fix my bad Verilog. I have alreayd learned to pass variables by name, how to use newer Verilog syntax to improve readability, and I am always looking for ways to improve. > > The two languages tend to promote slightly different styles of coding. > Take a simple register that may be interfaced to a micro bus, for > example. In VHDL, and especially in my own code, every piece of logic > that relates to the implementation of said register tends to be > encapsulated within a single process. OTOH I've seen plenty of Verilog > code that scatters different aspects of the implementation all > throughout the code, from the decode logic, the reading and the > writing. That's not to say you can't do either in both - it's just a > style that seems to permeate each language. I know you do VHDL, but I'd be interested in how to encapsulate all of that in Verilog. I typically do: assign ce = something & something else & ...; register reg1 (clock, reset, ce & !r_w, data_in, reg_data) and then somewhere else: data = (r_w & phi1 & ce ? reg_data : 8'bz); And I agree it's all over the place, but I am not sure how one better organizes it. I guess one could do: module register ( input reset, input clock, input ce, input oe, input data_in, output data_ram, output data_out ); but then you're synthesizing tri states in the module, and I understood that to be a no-no. > At the end of the day, most designs comprise the same few constructs > over and over again; the register interfaces, some memory/lookup, and > the state machines. Once you're adept in coding those, a lot of the > time you're simply rolling more of them. Whether it's Verilog or VHDL > makes little difference. > I would agree for the most part on this, as least based on my > knowledge. But, since I use registers a lot, I would love to clean > them up more so i did not have to do: assign ce =...; register reg0(...., ce & address[1:0] == 0 & phi2 & !r_w, ram0); register reg1(...., ce & address[1:0] == 1 & phi2 & !r_w, ram1); register reg2(...., ce & address[1:0] == 2 & phi2 & !r_w, ram2); register reg3(...., ce & address[1:0] == 3 & phi2 & !r_w, ram3); mux4_1 mux(address[1:0],ram0,ram1,ram2,ram3,mux_ram); assign data = (ce & r_w & phi2,mux_ram, 8'bz); -- Jim Brain email@example.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2016-04-25 18:00:02
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