Re: CPLDs/FPGAs toolchain

From: Mark McDougall <>
Date: Mon, 25 Apr 2016 23:24:23 +1000
Message-ID: <>
On 25/04/2016 1:33 AM, wrote:

> There seem to be a kind of a pattern emerging from what I read around
> the net: people who begin or do a little / occasionally / hobbyists
> tend to prefer Verilog as "easier", "more familiar", "more concise".
> People who do a lot of this / do it for living seem to gravitate
> towards VHDL.

In my _personal_ observations, I'd say that it's easier to write bad 
code in Verilog than it is in VHDL. I don't tend to see a lot of bad 
VHDL, but I've seen some shocking Verilog, though perhaps that's merely 
a symptom of your observation above?!?

The two languages tend to promote slightly different styles of coding. 
Take a simple register that may be interfaced to a micro bus, for 
example. In VHDL, and especially in my own code, every piece of logic 
that relates to the implementation of said register tends to be 
encapsulated within a single process. OTOH I've seen plenty of Verilog 
code that scatters different aspects of the implementation all 
throughout the code, from the decode logic, the reading and the writing. 
That's not to say you can't do either in both - it's just a style that 
seems to permeate each language.

I'd also venture to say that, on paper, VHDL looks more verbose than it 
strictly needs to be. Component declarations, for example, are rarely 

At the end of the day, most designs comprise the same few constructs 
over and over again; the register interfaces, some memory/lookup, and 
the state machines. Once you're adept in coding those, a lot of the time 
you're simply rolling more of them. Whether it's Verilog or VHDL makes 
little difference.


|              Mark McDougall              | "Electrical Engineers do it
|  <> |   with less resistance!"

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Received on 2016-04-25 14:00:03

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