Re: CPLDs/FPGAs toolchain

From: Michał Pleban <>
Date: Sun, 24 Apr 2016 11:14:25 +0200
Message-ID: <>
Hello! wrote:

> He put a disclaimer that those are his personal opinions. As for me - I read the descriptions and comparisons, look at the examples in both languages and the only advantage of Verilog I notice is a more familiar syntax. But I - personally - don't find it to be a real advantage. In any case - whether it's vim or emacs :-) - personal taste most probably.

Another personal opinion here: I did logic synthesis at the university
in both VHDL and Verilog. So after actually using both of them, not just
reading their description, I must say that I would absolutely prefer
Verilog. VHDL requires typing much more to achieve the same effect.
Think about Pascal syntax versus C syntax and you will get the idea.
After you write few hundred lines of "code", you will start appreciating


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Received on 2016-04-24 10:00:38

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