Re: CPLDs/FPGAs toolchain

What is the Synthesis I have heard mention of this?

One other question:  Why would CPLD need be used for Commodore, is this
because of the
5volt and other voltages and other things?

Thanks,
Terry Raymond

On Friday, April 22, 2016, Ingo Korb <ml@akana.de> wrote:

> silverdr@wfmh.org.pl <javascript:;> writes:
>
> > Since my practical experience with both CPLDs and FPGAs is currently
> > still wandering around $00, I am looking for something that would allow
> > me to do some designs and test / simulate those even before synthesizing
> > them for a particular chip. I recall my early experiences with
> > Atmel/Microchip tools that put me off so much as to delay my first micro
> > controller code more than a year. OTOH once I eventually set the free
> > toolchain up outside of their terrible (at least at that time) IDEs I
> > had a working device in a few hours. I am asking now because I wouldn't
> > like to repeat the story with my first CPLD ;-)
>
> My personal views:
>
> Xilinx ISE sucks and is now unsupported in favor of Vivado, but
> unfortunately Xilinx refuses to support any of their older devices in
> Vivado, so if you want to use a Spartan 6 or earlier or any CPLD, you'll
> need to use ISE. Its IDE is the only software which I've seen crash just
> by hitting Control-F (find) in the text editor - but fortunately this
> happens very rarely and most of the time wonky IDE behaviour can be
> fixed by closing the IDE and starting it again. In the background,
> everything is based on command-line tools and if you piece together a
> tool flow based on them things are mostly stable - though there are
> still annoyances like a segfault in one of the tools with certain
> of syntax errors in memory map description files (which you won't need
> unless you want to build a CPU-based system). Some people claim that the
> included simulator (ISim) is rather slow and very inferior to Mentor's
> ModelSim, but I'm quite happy with ISim. The free version of ISim is
> limited to a certain design size and slows down on purpose if that is
> exceeded, but I haven't run into that limit yet.
>
> Xilinx Vivado supports 7-series FPGAs only and is based around
> Eclipse. I haven't used it yet, but some people say that it sucks, which
> doesn't really surprise me.
>
> I don't have that much experience with Altera Quartus as I have with
> ISE, but it seems to suck less than ISE in some regards (less crashes)
> but more in others (no pre-inizialized inferred RAM, no command line
> data2mem-like utility). Altera includes a feature-limited copy of
> Modelsim with the free version of Quartus, but I haven't used it and
> thus can't comment on it.
>
> Lattice Diamond appears to suck a lot less than either Altera's or
> Xilinx' toolchains, but Lattice insists that you create a host-based
> license file that expires after a year even for the free edition. This
> may be because they include not only their own synthesis engine but also
> a copy of Synopsis' Synplify which some people claim is superior to the
> free offerings of at least Xilinx and Altera - but since I don't have a
> copy of Synplify that would work with X or A, I can't comment on
> that. For my relatively small design I did not see much difference
> between Synplify and Lattice's synthesis engine (except when I hit a bug
> in the latter) and I have never even tried to use the simulation tool
> included with Lattice Diamond because I just ported an existing design
> to a MachXO2 (nice chips, low cost, integrated config flash). Based on
> my limited experience with Diamond I would say that it seems to suck the
> least by far - I haven't managed to crash it even once and the synthesis
> times were drastically lower compared to Xilinx for the same design.
>
> For Lattice iCE40 FPGAs, you also have the option of using the IceStorm
> tool flow, which combines various open-source tools to compile Verilog
> to valid bit streams for this series of FPGAs. I have not tried that
> yet, so no comment. Simulation could probably be handled using
> verilator, which compiles Verilog to C plus a waveform viewer to display
> the results.
>
> If money is of no concern (prices in the "if you have to ask, you can't
> afford it" range), there are also synthesis and simulation tools from
> other vendors that target at least Xilinx and Altera FPGAs. Since Mentor
> and Cadence want quite a bit of money for them, I suspect that they must
> offer some advantage over the vendor's own tools (which are also quite
> expensive if you run into the limits of the free version), otherwise
> people probably wouldn't pay for them. =)
>
> Oh, and a small note about the language choice: VHDL is obviously
> superior to Verilog. It may be a bit more verbose, but it also offers a
> stricter type system, which can occasionally stop you from shooting your
> own foot. ;) Having access to record types (like "struct" in C) is also
> quite useful to make the code more concise and readable when you're
> dealing with things like a CPU bus - as far as I know no free synthesis
> tools supports SystemVerilog which would have an equivalent construct.
>
> -ik
>
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